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asahi kasei [AK4560A] ms0028-e-00 2000/05 - 1 - general description AK4560A is a 16bit stereo codec with a built-in microphone-amp, headphone-amp and speaker-amp. input circuits include microphone/line inputs selector, power supply for microphone, pre-amp, hpf-amp, eq-amp and alc (auto level control) circuit, and output circuits include lineout buffer, analog volume, headphone-amp and speaker-amp, therefore the AK4560A suits a portable application with a built-in lcd and etc. as multi-power-supply-system can be set a suitable power supply voltage in each block, the AK4560A is compatible with high performance and low power dissipation. the package is a 64pin lqfp, therefore, a new system can be a smaller board area than a current system is composed of 2 or 3 chips. feature 1. resolution: 16bits 2. recording function: 3-input selector (internal mic, external mic, line) pre-amp/eq-amp hpf-amp for wind-noise digital alc (auto level control) circuit fadein / fadeout digital hpf for offset cancellation (fc=3.7hz@fs=48khz) 3. playback function digital de-emphasis filter (tc = 50/15us, fs = 32khz, 44.1khz and 48khz) lineout buffer: +2dbv analog volume - 0db ~ -50db, mute headphone-amp - output level: -3.4dbv, thd+n = 1% speaker-amp with a built-in digital alc circuit - btl output - output power: 80mw @ 8 w beep and shutter signal inputs 4. analog through mode 5. power management 6. adc characteristics (lin ? alc1 ? admix ? adc) s/(n+d): 80db, dr=s/n: 86db 7. dac characteristics (dac ? lineout) s/(n+d): 82db, dr=s/n: 88db 8. master clock: 256fs/384fs 9. sampling rate: 8khz ~ 50khz 10. audio data interface format: msb-first, 2s compliment (ak4518/ak4550 compatible) adc: 16bit msb justified, dac: 16bit lsb justified 11. ta = -20 ~ 85 c 12. power supply codec, analog volume: 2.6 ~ 3.3v (typ. 2.8v) lineout, headphone-amp: 3.8 ~ 5.5v (typ. 4.5v) mic-amp: 2.6 ~ 5.5v (typ. 3.9v) speaker-amp: 3.8 ~ 4.3v (typ. 4.0v) 13. power supply current all circuits power-up: 32.5ma 14. package: 64pin lqfp, 0.5mm pitch 16bit codec with alc and mic/hp/spk-amps ak4560 a
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 2 - figure 1. AK4560A block diagram mvdd mvss 1 64 2 hpf 3 4 5 9 7 6 10 11 12 13 14 15 16 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 8 hpf int/ext hpf off on eq amp va agnd vref vcom int_mic_l ext_mic_l mvcm mrf int/ext pre amp int/ext pre amp eq amp int/ext 48 47 46 hpf on off hpf hpf 45 44 int_mic_r ext_mic_r mic block mic mix mix adc hpf adc ipga alc1 ain admix 43 42 41 40 39 38 37 36 35 34 33 svdd svss int/ext_det nd sp0 sp1 8 w 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 mute pd mclk lrck bclk cclk cs cdtio lout1 rout1 hpl hpr sdto sdti sht beep + vd dgnd + + + + + + lout lout lout lout lout lout lout lin rin hp hp hp hp hp hp hpp lo ut loutp loutp hp hp headphone- amp control register i/f clock divider audio i/f controller dac dac alc2 spps spps alcs beeps beeph aout1 aout1 aout0 aout0 vol analog volume mout mix speaker- block spkp spkp or hpp + + hvdd hvcm signal select power management power save mpwr beeph vol
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 3 - n ordering guide AK4560Avq -20 ~ +85 c 64pin lqfp (0.5mm pitch) akd4560a evaluation board n pin layout 60 59 58 57 56 55 54 53 pre_o_l pre_n_l ext_mic_l int_m ic_l mvss mvcm 45 44 43 42 41 40 39 38 37 eq_p_r eq_o_r hpf_p_r hpf_o_r mic_in_r svdd svss nd sp0 int_m ic_r pd 1 2 3 4 5 6 7 8 9 10 11 17 18 19 20 21 22 23 24 25 26 eq_p_l eq_o_l hpf_p_l hpf_o_l mic_in_l vcom vref agnd va rout2 min lin lout1 rin rout1 hvcm hvdd hpr hpl mute top view 12 opgr dgnd ext_mic_r 27 28 47 46 48 64 63 62 61 mrf mvdd eq_n_l lout2 mic_b int_ext_det sp1 vd 13 14 15 opgl beep 16 sht mout 52 51 50 49 mpwr pre_o_r eq_n_r pre_n_r 36 35 34 33 lrck bclk cclk mclk 29 30 sdto sdti cs 31 32 cdtio
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 4 - pin/function no. pin name i/o function power supply 6 vcom o common voltage output pin, 0.5 x va 7 vref o adc, dac reference level, 0.5 x va 8 agnd - analog ground pin 9 va - analog power supply pin, +2.8v 22 hvcm o lineout & hp-amp common voltage output pin, 0.5 x hvdd 23 hvdd - lineout & hp-amp power supply pin, +4.5v 27 vd - digital power supply pin, +2.8v 28 dgnd - digital ground pin 42 svss - speaker amp ground pin 43 svdd - speaker amp power supply pin, +4.0v 52 mpwr o mic power supply pin, 2.5v@mvdd=3.9v, idd=3ma(max) 55 mrf o mic power supply ripple filter pin 56 mvcm o mic block common voltage output pin, 0.5 x mvdd 57 mvss - mic block ground pin 58 mvdd - mic block power supply pin operation clock 29 sdto o audio serial data output pin 30 sdti i audio serial data input pin 34 bclk i audio serial data clock pin 35 lrck i input/output channel clock pin 36 mclk i master clock input pin mic block 1 eq_p_l i lch eq-amp positive input pin 2 eq_o_l o lch eq-amp output pin 3 hpf_p_l i lch hpf-amp positive input pin 4 hpf_o_l o lch hpf output pin 45 hpf_o_r o rch hpf output pin 46 hpf_p_r i rch hpf-amp positive input pin 47 eq_o_r o rch eq-amp output pin 48 eq_p_r i rch eq-amp positive input pin 49 eq_n_r i rch eq-amp negative input pin 50 pre_o_r 0 rch pre-amp output pin 51 pre_n_r i rch pre-amp negative input pin 53 ext_mic_r i external mic rch input pin 54 int_mic_r i internal mic rch input pin 59 int_mic_l i internal mic lch input pin 60 ext_mic_l i external mic lch input pin 61 mic_b i mic-amp bias pin 62 pre_n_l i lch pre-amp negative input pin 63 pre_o_l 0 lch pre-amp output pin 64 eq_n_l i lch eq-amp negative input pin note: all input pins should not be left floating.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 5 - control data interface 31 cdtio i/o control data input/output pin 32 cs i chip select pin 33 cclk i control clock input pin alc1 block 5 mic_in_l i lch mic input pin 18 lin i lch line input pin 20 rin i rch line input pin 44 mic_in_r i rch mic input pin dac 10 rout2 o rch #2 line output pin, -5.5dbv@va=2.8v 12 lout2 o lch #2 line output pin, -5.5dbv@va=2.8v 19 lout1 o lch #1 line output pin, +2dbv@va=2.8v, vol=+7.5db 21 rout1 o rch #1 line output pin, +2dbv@va=2.8v, vol=+7.5db analog volume 11 opgr i rch analog volume input pin 13 opgl i lch analog volume input pin headphone amp 24 hpr o rch headphone-amp output pin 25 hpl o lch headphone-amp output pin speaker amp block 16 mout o analog mixing output pin 17 min i alc2 input pin 38 sp0 o speaker amp positive output pin 40 sp1 o speaker amp negative output pin other functions 14 beep i beep signal input pin 15 sht i shutter signal input pin 26 mute i mute pin, l: normal operation, h: mute 37 pd i power down & reset pin, l: power-down & reset, h: normal operation 39 nd i noise decrease pin, l: disable, h: enable 41 int_ext_det i internal /external mic detect pin, l: internal mic, h: external mic note: all input pins should not be left floating.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 6 - absolute maximum rating (agnd, dgnd, mvss, svss=0v; note 1) parameter symbol min max units power supplies analog 1 (va pin) analog 2 (hvdd pin) mic (mvdd pin) digital (vd pin) speaker (svdd pin) | dgnd C agnd | (note 2) | mvss C agnd | (note 2) | svss C agnd | (note 2) va hvdd mic vd svdd d gnd1 d gnd2 d gnd3 -0.3 -0.3 -0.3 -0.3 -0.3 - - - 6.0 6.0 6.0 6.0 6.0 0.3 0.3 0.3 v v v v v v v v input current (any pines except supplies) iin - 10 ma analog input voltage (note 3) (note 4) vina1 vina2 -0.3 -0.3 va+0.3 mic+0.3 v v digital input voltage (note 5) (note 6) (note 7) vind1 vind2 vind3 -0.3 -0.3 -0.3 vd+0.3 hvdd+0.3 svdd+0.3 v v v ambient temperature ta -20 85 c storage temperature tstg -65 150 c maximum power dissipation (note 8) pd - 650 mw note 1. all voltage with respect to ground. note 2. dgnd and agnd, mvss and agnd, svss and agnd are the same voltage. note 3. analog input pins except ext_mic_l, ext_mic_r, int_mic_l, int_mic_r, pre_n_l, pre_n_r, eq_n_l, eq_n_r, eq_p_l, eq_p_r, hpf_p_l, hpf_p_r and mic_b pins. note 4. ext_mic_l, ext_mic_r, int_mic_l, int_mic_r, pre_n_l, pre_n_r, eq_n_l, eq_n_r, eq_p_l, eq_p_r, hpf_p_l, hpf_p_r and mic_b pins note 5. except int_ext_det, nd and mute pins note 6. mute pin note 7. int_ext_det and nd pins note 8. wiring density is 50% over. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommend operating conditions (agnd, dgnd, mvss, svss=0v; note 1) parameter symbol min typ max units power supplies analog 1 (va pin) analog 2 (hvdd pin) mic (mic pin) digital (vd pin) speaker (svdd pin) va hvdd mic vd svdd 2.6 3.8 2.6 2.6 3.8 2.8 4.5 3.9 2.8 4.0 3.3 5.5 5.5 3.3 4.3 v v v v v note 1. all voltage with respect to ground. * akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 7 - analog characteristics (ta=25 c; va=vd=2.8v, mvdd=3.9v, svdd=4.0v, hvdd=4.5v; agnd=dgnd=mvss=svss=0v; fs=48khz; input frequency = 1khz; measurement width = 20hz ~ 20khz; unless otherwise specified) parameter min typ max units pre-amp characteristics: input resistance (note 9) 70 100 130 k w maximum output voltage (note 10) -1 dbv gain +18 +26 +30 db load resistance 1 k w load capacitance (note 11) 20 pf eq-amp characteristics: (gain:0db) maximum output voltage (note 11) -1 dbv load resistance 1 k w load capacitance (note 11) 20 pf hpf-amp characteristics: (gain: 0db) maximum output voltage (note 10) -1 dbv load resistance 3 k w load capacitance (note 11) 20 pf mic block characteristics: measured via hpf_o_l/hpf_o_r (note 12) s/(n+d) (-10dbv output) 60 77 db output noise voltage (no signal input, rg = 1k w ) bw = 20hz ~ 20khz, a-weighted) (note 13) bw = 400hz ~ 30khz (note 14) -93 -92 -89 -88 dbv dbv interchannel isolation 70 90 db mic power supply characteristics: output voltage (no load) (note 15) 2.2 2.5 2.8 v output current 3ma note 9. int_mic_l, int_mic_r, ext_mic_l and ext_mic_r pins note 10. maximum output voltage is typically ( mvdd-1.3) v. note 11. when output pin drives some capacitive load, some resistor should be added in series between output pin and capacitive load. note 12. these values are measured via the following path. eq-amp and hpf-amp are a unity gain buffer. pre-amp (gain: +26db ? eq-amp (gain: 0db, not add signal of other channel) ? hpf-amp (gain: 0db) note 13. in case of the following path, output noise voltage is suitable value for -59.4db (typ) and -55.4dbv (min). mic block (gain: +26db, input from int_mic_l/int_mic_r pins) ? ipga (gain: +26db) + adc ? dac+lineout (gain: +7.5db, measured via lout1/rout1 pins) note 14. in the following path, if analog input signal is C70dbv (then analog output level is C10.5dbv at lineout), output noise voltage except the fundamental wave is suitable value for 58.4dbv(typ.) and C54.4dbv(min.). because it is not possible that each block of ipga, adc, dac and lineout output a distortion when the small signal level is input. mic block (gain: +26db, input from int_mic_l/int_mic_r pins) ? ipga (gain: +26db) + adc ? dac+lineout (gain: +7.5db, measured via lout1/rout1 pins) note 15. output voltage is typically (mvdd - 1.4) v.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 8 - parameter min typ max units alc1 characteristics (ipga): maximum input voltage (note 16) -0.5 dbv input resistance: mic(mic_in_l and mic_in_r pins) (note 17) line(lin and rin pins) (note 18) 5.6 117 9 184 13 260 k w k w mic line step size +26db ~ -10db -10db ~ -18db -18db ~ -30db -30db ~ -42db -42db ~ -54db +0db ~ -36db -36db ~ -44db -44db ~ -56db -56db ~ -68db -68db ~ -80db 0.1 0.1 0.1 - - 0.5 1 2 2 4 db db db db db adc analog input characteristics: alc1 = off resolution 16 bits input voltage (note 19) (note 20) (note 21) -6.3 -32.3 -5.5 -31.5 -4.7 -30.7 dbv dbv s/(n+d) (-2.0dbfs output) (note 20) (note 21) 74 68 80 74 db db dr (-60dbfs output, a-weighted) ( note 20) (note 21) 80 73 86 79 db db s/n (a-weighted) (note 20) (note 21) 80 73 86 79 db db interchannel isolation (note 20) (note 21) 80 80 100 100 db db interchannel gain mismatch (note 20) (note 21) 0.5 0.5 db db dac analog output characteristics: measured via out1/rout1. vol=+7.5db resolution 16 bits s/(n+d) (0dbfs input) 76 82 db dr (-60dbfs input, a-weighted) 82 88 db s/n (a-weighted) 82 88 db output voltage (note 19) +1.2 +2 +2.8 dbv interchannel isolation 80 100 db interchannel gain mismatch 0.5 db load resistance 10 k w load capacitance (note 22) 20 pf note 16. when alc1 is enabled, maximum input voltage becomes typically (va C 0.13v) vpp. e.g. 2.67vpp = -0.5dbv @ va = 2.8v note 17. input impedance of mic changes from 8k w to 10k w by setting gain value, typically. note 18. input impedance of line changes from 168k w to 200k w by setting gain value, typically. note 19. input/output voltage are proportional to va voltage. 0.54 x va. note 20. input from lin/rin pins. ain = 1. ipga = 0db. note 21. input from mic_in_l and mic_in_r pins. ain = 0. ipga = +26db. note 22. when output pin drives some capacitive load, some resistor should be added in series between output pin and capacitive load.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 9 - parameter min typ max units analog volume characteristics (opga): input resistance (opgl and opgr pins) (note 23) 44 110 205 k w step size: +0db ~ -16db -16db ~ -38db -38db ~ -50db 0.1 0.1 0.1 1 2 4 db db db headphone-amp characteristics: r l = 220 w (note 24) output voltage (fs-12db = -17.5dbv input) (note 19) -6.5 -5.7 -4.9 dbv s/(n+d) (-3.4dbv output) 40 53 db output noise voltage (opga=mute, a-weighted) -80 -74 dbv interchannel isolation 80 100 db interchannel gain mismatch 0.5 db load resistance 220 w load capacitance (note 22) 20 pf speaker-amp characteristics: r l = 8 w , btl, input from min pin, alc2=off output voltage -4 -2 0 dbv s/(n+d) (80mw output) 40 55 db s/n (a-weighted) 81 87 db load resistance 8 w load capacitance (note 22) 10 pf shutter input: (sht pin) maximum input voltage (note 19) -5.5 dbv input resistance 29 42 55 k w beep input: (beep pin) maximum input voltage (note 19) -7.5 dbv feed-back resistance 14 20 26 k w monaural input: (min pin) maximum input voltage (note 19) -5.5 dbv input resistance (note 25) 14 23 33 k w monaural output: (mout pin) ( note 26) output voltage (note 19) -6.3 -5.5 -4.7 dbv load resistance 10 k w load capacitance (note 22) 20 pf note 23. input impedance of opga changes from 63k w to 158k w by setting gain value, typically. note 24. input opgl/opgr pins. these values are measured via the following path. analog volume (opga=0db) ? monaural output ( mout pin) note 25. input impedance of min pin changes from 21k w to 25k w by setting alc2 gain value, typically. note 26. opgl/opgr pins are input to C5.5dbv. these values are measured via the following path. analog volume (opga=0db) ? monaural output ( mout pin)
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 10 - parameter min typ max units power supplies current power up ( pd = h) all circuit power up: (mic=ipga=adc=dac=vcom=hpp=spkp=loutp= 1) va+vd 19.0 28.5 ma mvdd (note 27) 6.5 9.8 ma hvdd:hp-amp normal operation (lout=hp= 1, no output) 3.5 5.3 ma svdd:spk-amp normal operation (spps= 1, no output) 3.5 5.3 ma alc1+admix+adc: (ipga=adc=vcom= 1) (note 28) va+vd 10.0 15.0 ma dac+lineout: (dac=loutp=vcom= 1) (note 29) va+vd 8.0 12.0 ma hvdd: lineout normal operation (lout= 1, no output) 1.5 2.3 ma power down ( pd = l) va+vd+hvdd+mvdd+svdd (note 30) 200 ua note 27. mpwr pin supplies 0ma. note 28. as vcom = 1, hvdd of power supply current is 0.5ma (typ.) and power supply current of mvdd is 0.5ma (typ.). note 29. as vcom= 1, power supply current is 0.5ma (typ.). note 30. in case of power-down, all digital input pins including clock (mclk, bclk and lrck) pins are held vd or dgnd. pd pin is held dgnd.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 11 - filter characteristics (ta=25 c; va=vd=2.6 ~ 3.3v; fs=48khz; de-emphasis = off) parameter symbol min typ max units adc digital filter (lpf): passband (note 31) 0.1db -1.0db -3.0db pb 0 - - 21.8 23.0 18.9 - - khz khz khz stopband (note 31) sb 29.4 khz passband ripple pr 0.1 db stopband attenuation sa 65 db group delay (note 32) gd - 17.0 - 1/fs group delay distortion d gd 0us adc digital filter (hpf): frequency response (note 31) -3.0db -0.56db -0.15db fr - - - 3.7 10 20 - - - hz hz hz dac digital filter: passband (note 31) 0.1db -6.0db pb 0 - 24.0 21.7 - khz khz stopband (note 31) sb 26.2 khz passband ripple pr 0.06 db stopband attenuation sa 43 db group delay (note 32) gd - 14.8 - 1/fs dac digital filter + analog filter: frequency response 0 ~ 20.0khz fr 0.5 db note 31. the passband and stopband frequencies scale with fs (system sampling rate). for example, adc is pb=0.454*fs (@-1.0db), dac is pb=0.454*fs (@-0.1db). note 32. the calculating delay time which occured by digital filtering, this time is from the input of analog signal to setting the 16 bit data of both channels on input register to the output register of adc. and this time include group delay of hpf. for dac, this time is from setting the 16 bit data of both channels on input register to the output of analog signal.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 12 - dc characteristics (ta=25 c; va=vd=2.6 ~ 3.3v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 1.5 - - - - 0.6 v v high-level output voltage iout=-200ua low-level output voltage iout=200ua voh vol vd-0.2 - - - - 0.2 v v input leakage current iin - - 10 ua switching characteristics (ta=25 c; va=vd=2.6 ~ 3.3v; c l =20pf) parameter symbol min typ max units control clock frequency master clock(mclk) 256fs: frequency pulse width low pulse width high 384fs: frequency pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh 2.048 28 28 3.072 23 23 12.288 18.432 12.8 19.2 mhz ns ns mhz ns ns channel select clock (lrck): frequency duty fs duty 8 45 48 50 50 55 khz % audio interface timing bclk period bclk pulse width low pulse width high lrck edge to bclk - (note 33) bclk - to lrck edge (note 33) lrck to sdto(msb) delay time bclk to sdto delay time sdti latch hold time sdti latch set up time tblk tblkl tblkh tlrb tblr tlrm tbsd tsdh tsds 312.5 130 130 50 50 50 50 80 80 ns ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdtio latch set up time cdtio latch hold time csn h time csn to cclk - cclk - to csn - cdtio output delay time csn - to cdto(hi-z) time (note 34) tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 50 50 150 50 50 70 70 ns ns ns ns ns ns ns ns ns ns reset timing pd pulse width pd - to sdto delay time tpdw tpdv 150 8224 ns 1/fs note 33. bclk rising edge must not occur at the same time as lrck edge. note 34. r l =1k w /10% change. (pull-up operates for vd)
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 13 - n timing diagram figure 2. clock timing figure 3. audio data input/output timing figure 4. write/read command input timing note:1. cdtio pin should not be left floating except read output timing as cdtio pin is input pin then. lrck bclk mclk tclkl 1/fclk t clkh 1.5v 0.6v 1/fs 1.5v 0.6v t blkl t blk t blkh 1.5v 0.6v lrck bclk sdto t bsd 1.5v 0.6v 1.5v 0.6v 50%vd t lrm t lrb t blr t sdh t sds sdti 1.5v 0.6v d15(msb) d14 1.5v tcckl tcckh tcds tcdh cs cclk cdtio(i) op1 a0 tcss op0 op2 0.6v 1.5v 0.6v 1.5v 0.6v hi- z(note 1)
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 14 - figure 5. read data input/output timing figure 6. write/read data input/output timing notes:1. cdtio pin should not be left floating except read output timing as cdtio pin is input pin then. 2. r l = 1k w /10% change. (pull-up operates for vd.) figure 7. reset timing 1.5v cs cclk cdtio(o) tdcd d1 d0 a4 a3 0.6v 1.5v 0.6v 50%vd hi- z (note 1) d2 1.5v cs cclk cdtio(i/o) tcsh d7 d6 d5 d4 0.6v 1.5v 0.6v tcsw tccz hi- z(note 2) pd 0.6v t pdw t pdv sdto 50%vd
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 15 - operation overview n system clock the clock which are required to operate are mclk (256fs/384fs), lrck (fs), bclk (32fs ~ ). the master clock ( mclk) should be synchronized with lrck but the phase is free of care. the mclk can be input 256fs or 384fs. when 384fs is input, the internal master clock is divided into 2/3 automatically. * fs is sampling frequency. when the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4560A may occur click noise. in case of dac, click noise is avoided by setting the inputs to 0. all external clocks (mclk, bclk and lrck) should always be present. if these clocks are not provided, the AK4560A may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. if the external clocks are not present, the AK4560A should be in the power-down mode. (refer to the power management mode.) n system reset AK4560A should be reset once by bringing pd pin l upon power-up. after the system reset operation, the all internal AK4560A registers become initial value. initializing cycle is 8224/fs=171.3ms@fs=48khz. during initializing cycle, the adc digital data outputs of both channels are forced to a 2's compliment, 0. output data of adc settles data equivalent for analog input signal after initializing cycle. this cycle is not for dac. as a normal initializing cycle may not be executed, nothing writes at address 02h during initializing cycle. n digital high pass filter the adc has hpf for the dc offset cancel. the cut-off frequency of hpf is 3.7hz (@fs=48khz) and it is -0.15db at 22hz. it also scales with the sampling frequency (fs).
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 16 - n audio interface format data is shifted in/out the sdti/sdto pins using bclk and lrck inputs. the serial data is msb-first, 2's compliment format, adc is msb justified and dac is lsb justified. lrck bclk ( 32fs ) sdto(o) sdti ( i ) 012 8910121315012 89101213150 15 1 14 4 876 0 32 11 14 1 5 15 14 4 876 0 321 5 14 11 15 13 bclk ( 64fs ) sdto ( o ) 0 1 2 3 14 15 17 18 31 0 1 2 14 15 17 18 31 0 15 1 14 0 15 14 1 2 1 15 sdti ( i ) 10 15 14 10 15 14 15:msb, 0:lsb lch data rch data dont care 21 13 dont care 16 0 16 3 13 3 13 13 3 figure 8. audio data timing n control register timing the data on the 3-wire serial interface consists of op-code (3bit), address (lsb-first, 5bit) and control data (lsb-first, 8bit). the transmitting data is output to each bit by of cclk, the receiving data is latched by - of cclk. writing data becomes effective by - of cs . reading data becomes hi-z (floating) by - of cs . cs should be held to h at no access. cclk always need 16 edges of - during cs . reading/writing of the address except 00h ~ 09h are inhibited. reading/writing of the control registers by except op1-0 = 11 are invalid. in case of reading data, nothing is written to d0 ~ d7 data. figure 9. control data timing cs cclk op0- op2: op- code (111:write, 110:read) 1 a0- a4: address d0- d7: control data 0 34567 9101112131415 28 cdtio d7 d6 d5 d4 d3 d2 d1 a4 a3 a2 a1 a0 op1 op0 op2 d0 "1" "x" "1"
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 17 - n register map the following registers are reset at pd pin = l, then inhibits writing. addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h signal select 1 0 0 admix aout1 aout0 ain hpf int/ext 01h signal select 2 spps alcs beeps lout mout beeph hp vol 02h power management control loutp spkp hpp vcom dac adc ipga mic 03h mode control 0 0 vol1 vol0 mono1 mono0 dem1 dem0 04h timer select fdtm1 fdtm0 ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 05h alc mode control 1 0 0 zelm lmat1 lmat0 fdatt ratt lmth 06h alc mode control 2 0 ref6 ref5 ref4 ref3 ref2 ref1 ref0 07h operation mode 0 0 stat nd alc2 fdin fdout alc1 08h input pga control 0 ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 09h output pga control 0 0 0 opga4 opga3 opga2 opga1 opga0 table 1. AK4560A register map signal select 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h signal select 1 0 0 admix aout1 aout0 ain hpf int/ext r/w rd r/w reset 0 0 0 0 1 0 0 0 int/ext: select internal / external mic (refer to figure 12 and figure 13.) 0: internal mic (reset) 1: external mic int/ext bit and int_ext_det pin are ored. when this function is controlled by int_ext_det pin, int_ext bit is fixed to 0. when this function is controlled by int/ext bit, int_ext_det pin is fixed to l. hpf: select hpf-amplifier 0: disable (reset) 1: enable when hpf bit is 0, hpf-amp becomes a unity gain buffer. when external mic (int/ext bit = 1 or int_ext_dec pin = h) is selected, hpf bit is ignored. ain: select input signal of alc1 and change gain table of ipga. 0: mic (reset) 1: line aout1-0: select input signal of lineout or analog volume (opga) on/off of dac is selected by aout0 bit and on/off of analog through mode is selected by aout1. 00: input signal is off. common voltage is output. 01:dac (reset) 10: analog through mode (output signal of alc1) 11: output signal of dac and analog through are mixed. admix: output signal of alc1 and input signal of sht pin are mixed. 0: disable (reset) 1: enable
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 18 - signal select 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h signal select 2 spps alcs beeps lout mout beeph hp vol r/w r/w reset 0 0 0 0 0 0 0 0 vol: select signal of analog volume (opga) to input to headphone-amp 0: off (reset) 1: on. output signal of analog volume is input to headphone-amp. hp: select output signal of headphone-amp 0: off. power-save-mode. output hvcm voltage (reset) 1: on beeph: select beep signal to input to headphone-amp 0: off (reset) 1: on. input beep signal to headphone-amp. mout: select monaural output (mixing = (l+r)/2). 0: off. output vcom voltage. (reset) 1: on lout: select lineout 0: off. power-save-mode. output hvcm voltage. (reset) 1: on beeps: select beep/shutter signal to input to speaker-amp 0: off (reset) 1: on. beep or shutter signal is input to speaker-amp. alcs: select output signal of alc2 to input to speaker-amp 0: off (reset) 1: on. output signal of alc2 is input to speaker-amp. spps: speaker-amp power-save-mode 0: power-save-mode sp0 pin becomes hi-z and sp1 pin is output to svdd/2 voltage. (reset) 1: normal operation
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 19 - power management control addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h power management control loutp spkp hpp vcom dac adc ipga mic r/w r/w reset 1 1 1 1 1 1 1 1 mic: mic block (pre-amp, eq-amp, hpf-amp and mpwr) power control. 0: off. output pins are hi-z. 1: on (reset) ipga: ipga (alc1) power control 0: off 1: on (reset) adc: adc power control 0: off. sdto pin is output l. 1: on (reset) when adc bit changes from 0 to 1, initializing cycle (8224/fs=171.3ms@fs=48khz) starts. after initializing cycle, digital data of adc is output. dac: dac power control 0: off 1: on (reset) vcom: common voltage (vcom, hvcm and mvcm) power control 0: off 1: on (reset) hpp: headphone-amp power control (including opga, beep and hp-amp) 0: off. output of headphone-amp becomes l (agnd). 1: on (reset) spkp: speaker block power control (including opga, beep, mout, alc2 and speaker-amp) 0: off. output of speaker-amp is hi-z. 1: on (reset) loutp: lineout power control 0: off. output pin is hi-z. 1: on (reset) analog volume (opga) are enabled when spkp bit = 1 or hpp bit = 1. these bits can be partially powered-down by on/off (1 / 0). when pd pin goes l, all the circuit in AK4560A can be powered-down regardless of these bits in the address. when bit in this address goes all 0, all the circuits in AK4560A can be also powered- down. but contents of registers are kept. when each block is operated, vcom bit must go 1. vcom bit can write 0 when all bits in this address can be 0. except the case of ipga=adc=dac=spkp=hpp= 0 or pd pin = l, mclk, bclk and lrck should not be stopped.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 20 - figure 10. power management control figure 11. analog power supply source of each block mic admix alc1 adc d0: mic d1:ipga d2:adc hp line d5:hpp d4:vcom d7:loutp mout spk alc2 d6:spkp vcom mpwr dac d3:dac out opga (*1) (*1:opga is enabled by contro lling hpp or spkp bit.) beep sht mic admix alc1 adc mvdd va va hp line hvdd va hvdd mout spk alc2 svdd vcom mpwr dac va out opga beep sht va va
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 21 - mode control addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h mode control 0 0 vol1 vol0 mono1 mono0 dem1 dem0 r/w rd r/w reset 0 0 1 0 0 0 0 1 dem1-0: select de-emphasis frequency the AK4560A includes the digital de-emphasis filter (tc = 50/15us) by iir filter. the filter corresponds to three sampling frequencies (32khz, 44.1khz and 48khz). the de-emphasis filter selected dem0 and dem1 registers are enabled for input audio data. dem1 dem0 mode 0 0 44.1khz 0 1 off 1 0 48khz 1 1 32khz reset table 2. de-emphasis frequencies mono1-0: select digital data to input to dac mono1 mono0 lout rout 0 0 lch rch 0 1 lch lch 1 0 rch rch 1 1 rch lch reset table 3. select digital data to input to dac vol1-0: lineout gain setting as signal level of lineout is different by va power supply voltage, a gain of lineout is set by vol1-0 bits. vol1 vol0 gain va voltage 1 0 +7.5db 2.8v 1 1 +6.9db 3.0v reset table 4. lineout volume setting
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 22 - timer select addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h timer select fdtm1 fdtm0 ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 r/w r/w reset 1 0 1 0 1 0 0 0 ltm1-0: alc1 limiter operation period at zero crossing disable (zelm = 1) the ipga value is changed immediately. when the ipga value is changed continuously, the change is done by the period specified by ltm1-0 bits. alc1 limiter operation period ltm1 ltm0 48khz 44.1khz 32khz 0 0 0.5/fs 10us 11us 16us 0 1 1/fs 21us 23us 31us 1 0 2/fs 42us 45us 63us 1 1 4/fs 83us 91us 125us reset table 5. alc1 limiter operation period at zero crossing disable (zelm = 1) wtm1-0: alc1 recovery waiting period a period of recovery operation when any limiter operation does not occur during alc1 operation. recovery operation is done at period set by wtm1-0 bits. when the input signal level exceeds auto recovery waiting counter reset level set by lmth bit, the auto recovery waiting counter is reset. the waiting timer starts when the input signal level becomes below the auto recovery waiting counter reset level. alc1 recovery operation waiting period wtm1 wtm0 48khz 44.1khz 32khz 0 0 512/fs 10.7ms 11.6ms 16.0ms 0 1 1024/fs 21.3ms 23.2ms 32.0ms 1 0 2048/fs 42.6ms 46.4ms 64.0ms 1 1 4096/fs 85.2ms 92.8ms 128.0ms reset table 6. alc1 recovery operation waiting period ztm1-0: zero crossing timeout at writing operation by up and alc1 recovery operation when ipga of each l/r channels do zero crossing or timeout independently, the ipga value is changed by up write operation or alc1 recovery operation zero crossing timeout period ztm1 ztm0 48khz 44.1khz 32khz 0 0 513/fs 10.7ms 11.6ms 16.0ms 0 1 1025/fs 21.4ms 23.2ms 32.0ms 1 0 2049/fs 42.7ms 46.5ms 64.0ms 1 1 4097/fs 85.4ms 92.9ms 128.0ms reset table 7. zero crossing timeout fdtm1-0: fadein/out cycle setting the fadein/out operation is done by a period set by fdtm1-0 bits when fdin or f dout bits are set to 1. when ipga of each l/r channel do zero crossing or timeout independently, the ipga value is changed. fadein/out period fdtm1 fdtm0 48khz 44.1khz 32khz 0 0 512/fs 10.7ms 11.6ms 16.0ms 0 1 1024/fs 21.3ms 23.2ms 32.0ms 1 0 2048/fs 42.6ms 46.4ms 64.0ms 1 1 4096/fs 85.2ms 92.8ms 128.0ms reset table 8. fadein/out period
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 23 - alc mode control 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h alc mode control 1 0 0 zelm lmat1 lmat0 fdatt ratt lmth r/w r/w reset 0 0 0 0 0 0 0 0 lmth: alc1 limiter detection level / recovery waiting counter reset level the alc1 limiter detection level and the alc1 recovery counter reset level are of uneven quality about 2db. lmth alc1 limiter detection level alc1 recovery waiting counter reset level 0 adc input 3 -6.0db -6.0db > adc input 3 -8.0db 1 adc input 3 -4.0db -4.0db >adc input 3 -6.0db reset table 9. alc1 limiter detection level / recovery waiting counter reset level ratt: alc1 recovery gain step during the alc1 recovery operation, the number of steps changed from current ipga value is set. for example, when the current ipga value is 30h, ratt = 1 is set, ipga changes to 32h by the alc1 recovery operation, the input signal level is gained by 1db (=0.5db x 2). when the ipga value exceeds the reference level (ref6-0), the ipga value does not increase. ratt gain step 01 12 reset table 10. alc1 recovery gain step setting fdatt: fadein/out att step during the fadein/out operation, the number of steps changed from current ipga value is set. for example, when the current ipga value is 30h, fdatt = 1 is set, ipga changes to 32h(at fadein operation) or 2eh (at fadeout operation) by the fadein/out operation, the input signal level is changed by 1db (=0.5db x 2). when the ipga value exceeds the reference level (ref6-0), the ipga value does not increase. fdatt att step 01 12 reset table 11. fadein/out att step setting lmat1-0: alc1 limiter att step during the alc1 limiter operation, when either lch or rch exceeds the alc1 limiter detection level set by lmth, the number of steps attenuated from current ipga value is set. for example, when the current ipga value is 68h in the state of lmat1-0 bit = 11, it becomes ipga = 64h by the alc1 limiter operation, the input signal level is attenuated by 2db (=0.5db x 4). when the attenuation value exceeds ipga = 00 (mute), it clips to 00. lmat1 lmat0 att step 00 1 01 2 10 3 11 4 reset table 12. alc1 limiter att step setting zelm: enable zero crossing detection at alc1 limiter operation 0: enable (reset) 1: disable in case of zelm = 0, ipga of each l/r channel do zero crossing or timeout independently, the ipga value is changed by alc1 operation. zero crossing timeout is the same as alc1 recovery operation. in case of zelm = 1, the ipga value is changed immediately.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 24 - alc mode control 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h alc mode control 2 0 ref6 ref5 ref4 ref3 ref2 ref1 ref0 r/w rd r/w reset 0 1 1 0 0 0 0 0 ref6-0: set the reference value at alc1 recovery operation during the alc1 recovery operation, if the ipga value exceeds the setting reference value by gain operation, ipga does not become the larger than the reference value. for example, when ref=30h, ratt=2, ipga=2fh and ipga will become 2fh + 2step = 31h by the alc1 recovery operation, but the ipga value becomes 30h as ref value is 30h. gain(db) data mic line step level 60h +26.0 +0.0 5fh +25.5 -0.5 5eh +25.0 -1.0 ::: 2ch +0.0 -26.0 2bh -0.5 -26.5 ::: 19h -9.5 -35.5 18h -10.0 -36.0 0.5db 73 17h -11.0 -37.0 16h -12.0 -38.0 ::: 11h -17.0 -43.0 10h -18.0 -44.0 1db 8 0fh -20.0 -46.0 0eh -22.0 -48.0 ::: 05h -40.0 -66.0 04h -42.0 -68.0 2db 12 03h -46.0 -72.0 02h -50.0 -76.0 01h -54.0 -80.0 4db 3 reset 00h mute mute 1 table 13. setting reference value at alc1 recovery operation
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 25 - operation mode addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h operation mode 0 0 stat nd alc2 fdin fdout alc1 r/w rd r/w reset 0 0 0 0 1 0 0 0 alc1: alc1 enable flag 0: disable (reset) 1: enable fdout: fadeout enable flag 0: disable (reset) 1: enable fdin: fadein enable flag 0: disable (reset) 1: enable * when fadein or fadeout operation is done, alc1 bit should always be 1. alc2: alc2 enable flag 0: disable 1: enable (reset) after initializing cycle (2048/fs=42.7ms@fs=48khz), alc2 is enabled. this initializing cycle starts when pd pin change l to h or spkp bit change from 0 to 1. nd: ref6-0 value of alc1 is decreased to C3.5db. 0: keep ref6-0 value of alc1 (reset) 1: decrease C3.5db from ref6-0 value of alc1 this bit and nd pin are ored. when this function is controlled by nd pin, nd bit is fixed to 0. when this function is controlled by nd bit, nd pin is fixed to l. stat: status flag 0: in case of alc1 (including fadein, fadeout and noise decreasing function) operation or initializing cycle. (reset) 1: manual mode stat bit is 0 during initilizing operation after exiting power-down by pd pin. after the finish of the initilizing operation, stat bit becomes 1. during the alc1 operation, stat bit becomes 1 after the max 1 att/gain operation is completed by internal state.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 26 - input pga control addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h input pga control 0 ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 r/w rd r/w reset 0 0 1 0 1 1 0 0 ipga6-0: input analog pga; 97 levels gain(db) data mic line step level 60h +26.0 +0.0 5fh +25.5 -0.5 5eh +25.0 -1.0 ::: 2ch +0.0 -26.0 2bh -0.5 -26.5 ::: 19h -9.5 -35.5 18h -10.0 -36.0 0.5db 73 17h -11.0 -37.0 16h -12.0 -38.0 ::: 11h -17.0 -43.0 10h -18.0 -44.0 1db 8 0fh -20.0 -46.0 0eh -22.0 -48.0 ::: 05h -40.0 -66.0 04h -42.0 -68.0 2db 12 03h -46.0 -72.0 02h -50.0 -76.0 01h -54.0 -80.0 4db 3 reset 00h mute mute 1 table 14. input gain setting
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 27 - output pga control addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h output pga control 0 0 0 opga4 opga3 opga2 opga1 opga0 r/w rd r/w reset 0 0 0 1 1 1 1 1 opga4-0: output analog pga; 32 level; 0db ~ -50db, mute. these bits can change volume of headphone-amps and speaker-amp. this volume includes zero crossing detection, and it does l/r channels independently. zero crossing timeout is proportional to sampling rate, to = 512/fs. 10.7ms = 512/fs@fs=48khz 16ms = 512/fs@fs=32khz data gain(db) step level 1fh +0 1eh -1 1dh -2 :: 10h -15 0fh -16 1db 17 0eh -18 0dh -20 :: 05h -36 04h -38 2db 11 03h -42 02h -46 01h -50 4db 3 reset 00h mute 1 table 15. att value of analog volume
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 28 - function detail n mic block mic block includes 2-inputs selectors, internal mic or external mic mode can be selected by mic bit. (refer to figure 12 and figure 13) figure 12. internal path at selecting internal mic mode (hpf off) figure 13. internal path at selecting external mic mode (hpf off) int_mic_l ext_mic_l + - + - pre amp hpf 60 59 62 61 3 4 + - eq amp 64 2 5 on off 63 1 from rch hpf int/ext int/ext hpf to alc1 int_mic_l ext_mic_l + - + - pre amp hpf 60 59 62 61 3 4 + - eq amp 64 2 5 on off 63 1 from rch hpf int/ext int/ext hpf to alc1
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 29 - 1. pre- amp pre-amp is non-inverting amplifier and internally biased to mvcm voltage with 100k w (typ.). gain value of pre-amp is adjusted by external resistor. gain (1+rf/ri) of pre-amp should use a range of +18 ~ 30db. an external capacitor needs to cancel dc gain. cut-off frequency is decided by a external input resistor (ri) and a capacitor (c). figure 14. pre-amp 2. eq-amp eq-amp is block to emphasize a stereo feeling at using internal mic mode. eq-amp can be emphasized by adding the output signal from pre-amplifier and the reverse channel differentially. when external mic mode is selected, eq-amp does not connect. 3. hpf-amp to cancel wind-noise, AK4560A has the hpf-amp which is non-inverting amplifier, 2 nd order high pass filter and gain of 0db. the hpf-amp can be on/off by controlling the internal registers. in case of off, hpf-amp becomes a unity gain buffer. this hpf-amp can use when internal mic mode is selected. in case of external mic mode, the control of hpf-amp is invalid and becomes a unity gain buffer. 4. power supply for mic power supply for microphone is supplied from mpwr pin. output voltage is mvdd C 1.4v (typ) . for example, mpwr pin outputs 2.5v at mvdd = 3.9v. and mpwr pin can supply the current until 3ma. when mic bit is 0, the power supply current can be stopped. int_mic_l ext_mic_l + - pre amp 60 59 62 63 c ri rf
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 30 - n shutter signal input 1. recording when admix bit is 1, input signal from sht pin is attenuated to C4.5db internally and is mixed to output signal from alc1 by a gain of 0db. input impedance of sht pin is 42k w (typ.). when admix bit is 0, output signal of alc1 is input to adc by a gain of 0db. figure 15. admix block diagram 2. playback when beeps bit is 1, input signal from sht pin can be input to speaker-amp. this signal level can be adjusted by an external resistor (r2). an internal resistor value (rf) is 20k 30% w . for example, when r2 is 20k w , the final output level from speaker-amp becomes 20log 10 (20k/20k) db + 5.6db (speaker-amp) = +5.6db. ( refer to figure 16) n beep input when beeph bit is 1, input signal from beep pin can be input to headphone-amp. when beeps bit is 1, input signal from beep pin can be input to speaker-amp. this signal level can be adjusted by an external resistor (r1). an internal resistor value (rf) is 20k 30% w . for example, when r1 is 20k w , the final output level from headphone-amp becomes 20log 10 (20k/20k) db + 11.8db (headphone-amp block) = +11.8db. ( refer to figure 16) figure 16. block diagram of beep and sht pin + - adc alc1 sht pin gain=0db gain =-4.5db admix bit + - beep sht r1 to admix to spk or hp- amp rf=20k w r2
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 31 - n analog volume (opga) the AK4560A includes the 0db ~ -50db & mute analog volume with zero crossing detection for headphone and speaker. zero crossing is detected on l/r channels independently. zero crossing timeout (to) is proportional to sampling rate. to=512/fs@fs=48khz=10.7ms. opga is not written during counting zero crossing timers. in case of writing control register continually, the change of opga should be written after zero crossing timeout and over. if opga is changed by writing to control register before zero crossing detection, opga value of l/r channels may not give a difference level. usually, to remove the offset of dac, it needs a capacitor (ca) between lout2/rout2 and opgl/opgr. the cut-off frequency is decided by capacity of ca and input impedance (typ. 110k w ) of opgl/opgr. power supply for analog volume enables when speaker or headphone of power management bits is 1. (spkp bit = 1 or hpp bit = 1) the initial value is 0db at exiting power-down. figure 17. connect lout2/rout2 with opgl/opgr n line input in case of line input, input impedance of lin/rin is 184k w (typ.) and centered around the vcom voltage. when input voltage is +2dbv, lin/rin pins should be input to C5.5dbv@va=2.8v and less after dividing resistors externally. when lin bit is 1, line input is selected. then ipga table of alc1 is changed to line side. figure 18. example of linein at va=2.8v opga lout2/rout2 ca typ.110k w opgl/opgr alc1 line input typ.184k w lin/rin 22k w 27k w
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 32 - n mute pin function when mute pin is h, output signals of lineout, headphone and speaker is muted by force, and these signals are output to common voltage. then switches of aout1-0, vol, beeph, alcs and beeps become off by force. when mute pin is l, these output signals are normal operation. n analog through mode this mode can be input to playback circuits after adding alc1 output signal and shutter signal. this mode can be controlled by aout1-0 bits. n noise decreasing function when nd pin is h or nd bit is 1, the setting reference value of alc1 (ref6-0 bits) is decreased to C3.5db. then this mode is doing at every 1step with zero crossing detection. the time constant is about 12sec@fs=32khz and 8sec@fs=48khz. when nd pin (or nd bit) changes from h (or 1) to l (or 0), the current reference value operates toward the setting reference value of alc1. then this mode is doing at every 1step with zero crossing detection. the time constant is about 3sec@fs=32khz and 3sec@fs=48khz. in case of doing the fadein/fadeout operation during noise decreasing operation, the fadein/fadeout operation starts from the current ipga value.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 33 - n lineout the signals of dac or analog through mode are gained to +7.5db (@va= 2.8v, vol1-0 bit = 10, refer to figure 22) internally, and its signal is output from lineout. this gain can be changed by vol1-0 bits. output level of lineout is +2dbv and centered hvcm voltage. load resistance is min. 10k w . (refer to figure 19) power supply voltage for lineout is supplied from hvdd voltage. the supplied hvdd voltage does not change output level of lineout. but if hvdd voltage is low, a distortion characteristic of lineout is bad. lout1 and rout1 outputs are muted by lout bit. then lout1 and rout1 pins output hvcm voltage and enter power-save-mode. (refer to figure 20). when loutp bit is 0, lout1 and rout1 pins become power-down-mode and output signal is hi-z. (refer to figure 21) when pd pin changes from l to h after power-up, lout1 and rout1 pins become power-save-mode. in power-save-mode, lout1 and rout1 pins gradually become hvcm voltage via an internal resistor (r1: typ.200k w ) from hi-z to decrease a pop noise. and when power off, the pop noise can be decreased by controlling via power- save-mode. figure 19. lineout normal operation figure 20. lineout power-save-mode figure 21. lineout power-down-mode + - r1 c1 r2 lout1/rout1 lout lout lout lout loutp + - r1 c1 r2 lout1/rout1 lout lout lout lout loutp + - r1 c1 r2 lout1/rout1 lout lout lout lout loutp
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 34 - n headphone-amps power supply voltage for headphone-amp is supplied from hvdd pin and centered around hvcm voltage. load resistance of headphone output is min.220 w . (refer to figure 23). output level of headphone-amp is gained to +11.8db internally, and thd+n is 1% at C3.4dbv(1.9vpp) output level. (refer to figure 22) figure 22. lineout and headphone-amp level diagram (@va=2.8v,opga=-8db,vol1-0=+7.5db) 0dbv - 10dbv - 20dbv +10dbv - 30dbv dac lineout(high) lineout(low) analog volume +11.8db - 13.7dbv alc2 -10dbv - 17.5dbv - 17.5dbv opga = - 8db - 25.5dbv hp- amp +7.5db +7.5dbv +2dbv -5.5dbv - 17.5dbv +7.5dbv - 10.0dbv -5.5dbv +11.8db +6.3dbv - 8db - 25.5dbv +11.8db - 13.7dbv fs- 12db fs- 12db fs - 3.4dbv thd+n=1%
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 35 - when hp bit is 0, output signal is muted and enter the power-save-mode. then hpl and hpr pins output hvcm voltage. (refer to figure 24) when hpp bit is 0, headphone-amp is powered down perfectly. then hpl and hpr pins go l (agnd). (refer to figure 25) when pd pin changes from l to h after power-up, hpl and hpr pins become power-save-mode. in power- save-mode, output voltage of hpl and hpr pins gradually change from agnd to hvcm voltage by the time constants of an internal resistor (r2: typ.10k w ) and an external capacitor (c1). (refer to figure 24) in case of entering the normal operation mode after that, hp bit changes from 0 to 1. in the power-down-mode ( pd pin = l or hpp bit = 0), output voltage of hpl and hpr pins gradually change from agnd to hvcm voltage by the time constants of an internal resistor (r2:typ.10k w ) and an external capacitor (c1). (refer to figure 25) figure 23. headphone-amps normal operation figure 24. headphone-amps power-save-mode figure 25. headphone-amps power-down-mode + - r1 c1 r2 hpl/hpr hp hpp hp hp hp + - r1 c1 r2 hpl/hpr hp hpp hp hp hp + - r1 c1 r2 hpl/hpr hp hpp hp hp hp
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 36 - n speaker block the output signal from analog volume is converted into a monaural signal, its signal is input to speaker-amp via alc2 circuit. this speaker-amp is a monaural output by btl, can be output to maximum 80mw at 8 w . (refer to figure 26) speaker blocks (mout, alc2 and speaker-amp) can be powered on/off by controlling spkp bit. when spkp bit is 0, mout, sp0 and sp1 pins go hi-z. (refer to figure 28) when spps bit is 0, speaker-amp becomes power-save-mode. (refer to figure 27) then sp0 pin goes hi-z and sp1 pin is output to svdd/2 via r1 (typ.100k w ). when pd pin changes from l to h after power-up, sp0 and sp1 pins become power-save-mode. in power-save- mode, sp0 and sp1 pins gradually become hvcm voltage via an internal resistor (r1: typ.200k w ) from hi-z to decrease a pop noise. and when power off (spkp = 0), the pop noise can be decreased by controlling via power-save-mode. figure 26. speaker-amp normal operation figure 27. speaker-amp power-save-mode + - 8 w sp0 + - r1 spps spps spps spps sp1 spps spps spkp or spkp + - 8 w sp0 + - r1 spps spps spps spps sp1 spps spps spkp or spkp
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 37 - figure 28. speaker-amp power-down-mode 1. monaural output both l/r channels of output signal from analog volume (opga) are mixed at (l+r)/2. when mout bit is 0, these signals can be off. then mout pin outputs vcom voltage. load impedance is 10k w (min.). when spkp bit is 0, mout pin becomes power-down-mode and outputs hi-z. 2. alc2 input resistance of alc2 is 23k w (typ.) and centered around vcom voltage, and input signal level is C5.5dbv. (refer to figure 29) limiter detection level is not related to power supply voltage, output level is limited by the alc2 circuit when input signal exceeds C7.5dbv (=fs-2db@va=2.8v) and over. when the continuous signal of C7.5dbv and over is input to the alc2 circuit, the change period of alc2 limiter operation is 2/fs=42us@fs=48khz and the attenuation level is 0.5db/step. the alc2 recovery operation is always detected by zero crossing operation and gains 1db/step. the alc2 recovery operation is done until input level of speaker-amp goes to C9.5dbv(=fs-4db@va=2.8v). the alc2 recovery operation period is fixed to 2048/fs=42.7ms@fs=48khz. in case of inputting signal between C7.5dbv and C9.5dbv, the alc2 limiter or recovery operations are not done. when pd pin changes from l to h or spkp bit changes from 0 to 1, the initilizing cycle (2048/fs = 42.7ms @fs=48khz) starts. alc2 is disabled during initilizing cycle, alc2 starts after finishing the initilizing cycle. parameter alc2 limiter operation alc2 recovery operation operation start level -7.5dbv -9.5dbv fs=48khz 2/fs = 42us 2048/fs = 42.7ms period fs=32khz 2/fs = 63us 2048/fs = 64ms zero-crossing detection no yes(timeout = 2048/fs ) att/gain 0.5db step 1db step table 16. content of alc2 + - 8 w sp0 + - r1 spps spps spps spps sp1 spps spps spkp or spkp
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 38 - figure 29. speaker-amp output level diagram (va=2.8v, opga = -8db, vol1-0=+7.5db) 0dbv - 10dbv -20dbv - 30dbv dac lineout(high) lineout(low) analog volume alc2 -10dbv -17.5dbv -17.5dbv opga = - 8db - 25.5dbv +7.5db -5.5dbv - 17.5dbv -5.5dbv -8db -25.5dbv +18db fs- 12db fs- 12db fs spk hp- amp - 17.5dbv fs- 4db - 5.5dbv -8db - 13.5dbv fs- 2db -7.5dbv - 9.5dbv -2db - 6db -0.4db +5.6db - 7.9dbv -1.9dbv single- ended full-differential
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 39 - n alc1 operation 1. alc1 limiter operation during the alc1 limiter operation, when either lch or rch exceed alc1 limiter detection level (lmth), ipga value is attenuated by alc1 limiter att step (lmat1-0) automatically. then the ipga value is changed commonly for l/r channels. in case of zelm = 1, timeout period is set by ltm1-0 bits. the operation for attenuation is done continuously until the input signal level becomes lmth or less. after finishing the operation for attenuation, if alc1 bit does not change into 0, the operation of attenuation repeats when the input signal level exceed lmth. (refer to figure 30) in case of zelm = 0, timeout period is set by ztm1-0 bits. the ipga value is attenuated by zero crossing detection automatically. (refer to figure 31) the alc1 operation corresponds to the impulse noise in additional to the alc operation of ak4516a. when the impulse noise is input, the alc1 recovery operation becomes the faster period than a normal recovery operation. [explanation for alc1 operation] recovery waiting counter reset level (lmth) limiter detection level(lmth) att level (lmat1-0) (1) 2db att level (lmat1-0) att level (lmat1-0) limiter update period (ltm1-0) limiter finish limiter starts figure 30. disable alc1 zero crossing detection (zelm = 1) (1). when the signal is input between 2db, the AK4560A does not operate the alc1 limiter and recovery.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 40 - (3) zero crossing timeout (ztm1-0) att level (lmat1-0) att level (lmat1-0) (3) zero crossing timeout (ztm1-0) limiter detection level (lmth) limiter detection level (lmth) (1) (1) (2) (2) recovery waiting counter reset level (lmth) figure 31. in case of continuing the limiter operation (zelm = 0) (1) when the input level exceeds the alc1 limiter detection level, the alc1 limiter operation starts. zero crossing counter starts at the same time. (2) zero crossing detection. when the input signal is detected, the ipga value is attenuated until the value set by lmat1-0 and the alc1 limiter operation is finished. (3) zero crossing timeout is set by ztm1-0 bits. but the first zero crossing timeout cycle after starting the limiter operation may be the short cycle by the state of the last zero crossing counter. (for example, in case of doing the limiter operation during the recovery operation)
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 41 - 2. alc1 recovery operation the alc1 recovery operation waits until a time of setting wtm1-0 bits after completing the alc1 limiter. if the input signal does not exceed lmth C 2db, the alc1 recovery operation is done. the ipga value increases automatically by this operation up to the set reference level (ref6-0 bits). then the ipga value is set for l/r commonly. the alc1 recovery operation is done at a period set by wtm1-0 bits. when l/r channels are detected by zero crossing operation during wtm1-0, the alc1 recovery operation waits until wtm1-0 period and the next recovery operation is done. during the alc1 recovery operation, when either input signal level of lch or rch exceeds the alc1 limiter detection level (lnth), the alc1 recovery operation changes into the alc1 limiter operation immediately in case of (recovery waiting counter reset level) input signal < limiter detection level during the alc1 recovery operation, the waiting timer of alc1 recovery operation is reset. therefore, in case of (recovery waiting counter reset level) > input signal, the waiting timer of alc1 recovery operation starts. during recovery counter reset limiter detection level (lmth) recovery waiting counter reset level (lmth) zero crossing detect wtm counter starts wtm counter starts wtm counter starts ztm counter starts ztm counter starts (1) (2) (2) wtm counter starts (2) figure 32. the transition from the limiter operation to the recovery operation (1). when the input signal is below the alc1 recovery waiting counter reset level, the alc1 recovery operation waits the time set by wtm1-0 bits. if the input signal does not exceed the alc1 limiter detection level or the alc1 recovery waiting counter reset level, the alc1 recovery operation is done only once. (2). the ipga value is changed by the zero crossing operation in alc1 recovery operation, but the next counter of the alc1 recovery waiting timer is also starting. other: when a channel of one side enters the limiter operation during the waiting zero crossing, the present alc1 recovery operation stops, according as the small value of ipga (a channel of waiting zero crossing), the alc1 limiter operation is done. when both channels are waiting for the next alc1 recovery operation, the alc1 limiter operation is done from the ipga value of a point in time. during the alc1 operation, the value of writing in ipga6-0 bits is ignored.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 42 - (1) recovery waiting counter reset level (lmth) or reference value of recovery operation (ref6-0) (2) zero crossing timeout (ztm1-0) & recovery waiting time (wtm1-0) gain level (ratt) zero crossing detect limiter detection level (lmth) figure 33. the continuous alc1 recovery operation (1). when the input signal exceeds the alc1 recovery waiting counter reset level, the alc1 recovery operation stops, the alc1 recovery operation is repeated when input signal level is below lmth again. when the ipga value by repeating the alc1 recovery operation reaches the reference level (ref6-0 bits), the alc1 recovery operation stops also (2). ztm bit sets zero crossing timeout and wtm bit sets the alc1 recovery operation period. when the alc1 recovery waiting time (wtm1-0 bits) is shorter than zero crossing timeout period of ztm1-0 bit, the alc1 recovery is operated by the zero crossing timeout period of ztm1-0 bit. therefore, in this case the auto recovery operation period is not constant. 3. alc1 operation off (alc1 bit = 0) the zero crossing detection of ipga is done to l/r channels independently. zero crossing timeout is set by ztm1-0 bits. when the control register is written from up, the zero crossing counter for l/r channels commonly is reset and its counter starts. when the signal detects zero crossing or zero crossing timeout, the written value from up becomes a valid for the first time. in case of writing to the control register continually, the control register should be written by an interval more than zero crossing timeout. if an appointed interval is written, there is possible to the different value the ipga value of l/r channels for example, when the present ipga value is updated by zero crossing detection in a channel of one side and other channel is not updated, if the new data is written in ipga, the updated channel is keeping the last ipga value and other channel is updated to a new ipga value by the last zero crossing counter. therefore, zero crossing counter does not reset when the zero crossing detection is waiting.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 43 - during alc1 operation, the following registers are inhibits. ltm1-0, lmth, lmat1-0, wtm1-0, ztm1-0, ratt, ref6-0 manual-mode wr ( power mana g ement control & si g nal select re g isters ) wr ( lmat1-0 , ratt , lmth ) wr ( ref6-0 ) alc1 operation wr ( alc1= 1 ) wr ( ipga6-0 ) wr ( ztm1-0 , wtm1-0 , ltm1-0 ) wr ( alc1= 0 ) rd ( stat ) finish alc1-mode and become manual-mode finish alc1 mode? stat = 1? * the value of ipga should be the same or smaller than refs. ye s ye s no no figure 34. registers set-up sequence at alc1 operation
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 44 - n fadein mode in fadein mode, the ipga value is increased at the value set by fdatt when fdin bit changes from 0 to 1. the update period can be set by fdtm1-0 bits. the fadein mode is always detected by the zero crossing operation. this operation is kept over the ref value or until the limiter operation at once. if the limiter operation is done during fadain cycle, the fadein operation becomes the alc operation. note: when fdin and fdout bits are 1, fdout operation is enabled. ipga ouput alc1 bit fdin bit (1) (2) (3) (4) (5) figure 35. example for controlling sequence in fadein operation (1) wr (alc1 = fdin = 0): the alc1 operation is disabled. to start the fadein operation, fdin bit is written in 0. (2) wr (ipga = mute): the ipga output is muted. (3) wr (alc1 = fdin = 1): the fadein operation starts. the ipga changes from the mute state to the fadein opera tion. (4) the fadein operation is done until the limiter detection level (lmth) or the reference level (ref6-0). after completing the fadein operation, the AK4560A becomes the alc1 operation. (5) fadein time can be set by fdtm1-0 and fdatt bits e.g. fdtm1-0 = 1024/fs @ fs =48khz = 21.3ms, fdatt = 1step (96 x fdtm1-0) / fdatt = 96 x 21.3ms / 1 = 2.04s
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 45 - n fadeout mode in fadeout mode, the present ipga value is decreased until the mute state when fdout bit changes from 0 to 1. this operation is always detected by the zero crossing operation. if the large signal is input to the alc1 circuit during the fadeout operation, the alc1 limiter operation is done. however a total time of the fadeout operation is the same time, even if the limiter operation is done. the period of fadeout is set by fdtm1-0 bits, a number of step can be set by fdatt bit. when fdout bit changes into 0 during the fadeout operation, the alc1 operation start from the preset ipga value. when fdout and alc1 bits change into 0 at the same time, the fdout operation stops and the ipga becomes the value at that time. note: when fdin and fdout bits are 1, fdout bit is enabled. ipga output alc1 bit fdout bit (1) (5) (6) (7) (4) (3) (2) (8) figure 36. example for controlling sequence in fadeout operation (1) wr (fdout = 1): the fadeout operation starts. then alc1 bit should be always 1. (2) fadeout time can be set by fdtm1-0 and fdatt bits. during the fadein operation, the zero crossing timeout period is ignored and becomes the same as the fadein period. e.g. fdtm1-0 = 1024/fs @ fs =48khz = 21.3ms, fdatt = 1step (96 x fdtm1-0) / fdatt = 96 x 21.3ms / 1 = 2.04s (3) the fadeout operation is completed. the ipga value is the mute state. if fdout bit is keeping 1, the ipga value is keeping the mute state. (4) analog and digital outputs mutes externally. then the ipga value is the mute state. (5) wr (alc1 = fdout = 0): exit the alc1 and fadeout operations (6) wr (ipga): the ipga value changes the initial value (exiting mute state). (7) wr (alc1 = 1, fdout = 0): the alc1 operation restarts. but the alc1 bit should not write until completing zero crossing operation of ipga. (8) release a mute function of analog and digital outputs externally.
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 46 - package n package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate 12.00.3 0.210.05 0.170.05 12.00.3 1 16 17 32 33 48 49 64 0.10 0.5 1.70max 0.100.10 0 ~ 10 0.450.2 10.0 64pin lqfp(unit:mm) 1.40 0.10 m 1.0
asahi kasei [AK4560A] ms0028-e-00 2000/05 - 47 - marking - asashi kasei logo - marketing code: AK4560Avq - date code: xxxxxxx (7 digits) first 4 digits: weekly code, remains 3 digits: code management in office - country of origin: japan important notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. 1 ak4560vq xxxxxxx japan

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